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HV9606
Initial Release
HV9606 Current-Mode PWM Controller with Supervisor
Features
Synchronous Forward, Forward, and Flyback Controller Lowest External Parts Count, Smallest Magnetics Eliminates Bootstrap Transformer Winding Supervisor Circuit Reduces Output Capacitance* up to 40% Supervisor Circuit Functions as P Supply Monitor and POR 15V to 250V Start-Up Regulator with START/STOP Control <1mA Operating, <6A Standby Input Current VDD Powered Operation down to 2.9V Charge Pump Gate Drive Supply Programmable Soft Start Under Voltage Lockout with Programmable Hysteresis <50% Duty Cycle Operation 15kHz to 400kHz Fixed Frequency PWM Operation Fault Tolerant Peer-to-Peer Synchronization Precision !1% Band Gap Voltage Reference Current Sense Leading Edge Blanking Small SSOP-20 Footprint *For short duration line loss, supervisor disables soft start if output within tolerance when VIN returns and thus reduces holdup requirements.
General Description
The HV9606 PWM controller allows the design of high efficiency (>90%) power supplies for distributed board mounted power (BMP) applications. Due to its high frequency capability it can provide high currents (20A @ 3.3V) with small transformers and due to its low internal operating voltage and current is also able to achieve high efficiencies in low power applications. The HV9606 utilizes fixed frequency current mode control with duty cycle internally limited to <50%. It supports both isolated and nonisolated topologies and provides all the necessary functions to implement a flyback, forward or synchronous forward converter with a minimum of external parts. Due to its low VDD operation the bootstrap magnetic winding is eliminated in non-isolated topologies. An on chip charge pump generates the gate drive voltage for driving an external N-channel MOSFET and eliminates the need for clamping by offering 250V immunity to high voltage transients common in telecom and network systems. It conforms to the requirements of IEEE 802.3 Powered Ethernet and ETR-080 ISDN specifications. The oscillator is programmable and provides fault tolerant peer-topeer synchronization to other similar circuits or master clock. The chip draws almost no current (<6A @ VIN < 20V) until the programmable START/STOP thresholds of the start-up regulator are satisfied. It can also be powered via the VDD pin, rather than the VIN pin, in the range of 2.9V to 5.5V. Other functions include leading edge current sense blanking, programmable SOFT START, precision !1% band gap reference and a SUPERVISOR CIRCUIT. The SUPERVISOR can provide housekeeping functions such as P supply monitoring and reset, soft start inhibit for rapid restart on short duration input voltage interruption. It also minimizes input and output capacitance requirements.
Applications
Powered Ethernet and VoIP Terminals Cable Modems and Amplifiers ISDN Network Terminations, Terminals and Adapters Network Equipment Servers, PCs and Peripheral Equipment Telecommunication Systems and Terminals Distributed Board Mounted Power Battery Backup Systems Portable Power Applications Automotive and Heavy Equipment
Typical Application Circuit
10W Non-Isolated 48V to 3.3V Flyback Converter
R3 R2 C2 C9
1
VDD STATUS
20
Q1
2
START SENSE
19
To uP RESET Pin.
R1
3
STOP
FB
18
C4
5
REF
HV9606
+48V
C7
4
Vin COMP
C8 R6 T1 D1 R7 C10
17
NI
16
+3.3V
6
SS
CA
15
C3
7
SYNC
C6
CB
14
C1
R4
8
RT VX2
13
C5
9
SGND GATE
M1
R8
R10
12
10
PGND
CS
11
R9 R5
GND To SYNC pin of other HV9606 PWMs.
GND
1 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Electrical Characteristics
Symbol (-40C TA +85C unless otherwise noted) Min Typ Max Units Conditions Parameter
Pre-Regulator/Start-up
VIN IIN IIN VDD(REG) UVLOVDD UVLOVDD Regulator input voltage Input leakage current Input leakage current Regulator output voltage VDD Under voltage lockout threshold VDD Under voltage lockout hysteresis 2.8 2.7 100 2.9 2.8 15 250 6 50 3.0 2.9 200 V A A V V mV VIN 20V, Start = 0V, Stop = 0V VIN = 250V Vin < 120V VDD rising
Supply
VDD IDD VVX2 UVLOVX2 UVLOVX2
(Test Condition: 0.1F CA to CB and 0.1F VX2 to PGND) Operating range Supply current Gate drive charge pump supply VX2 Under voltage lockout threshold VX2 Under voltage lockout hysteresis 1.8xVDD 4.5 0.4 2.9 1.0 5.5 1.5 V mA V V V GATE open, fOSC = 50 kHz, VDD = 3.3V
Start/Stop Control
VSTART VSTOP(MAX) VSTOP ISTART ISTOP Start threshold Maximum voltage Stop threshold Start input current Stop input current (Test condition: VVX2 = 5V) VVX2-0.2 0.15 30 30 50 50 V V nSec nSec IGATE = 10mA IGATE = -10mA CLOAD = 250pF CLOAD = 250pF 6.44 7.00 6.44 7.00 7.56 13 7.56 50 50 V V V nA nA VIN falling, VSTART = 0V 6.44V 6.44 VSTART VSTOP 7.56V, VSTOP is open 7.56V, VSTART to 10V via 10k VIN rising
MOSFET Driver Output
VGATE(HIGH) VGATE(LOW) tR tF
Output high voltage Output low voltage Rise time Fall time
Oscillator
fOSC fOSCRANGE TC f/f Initial accuracy Oscillator Frequency Range Temperature coefficient Voltage stability 30 100 1 10 800 300 2 % kHz PPM/C fOSC = 100 kHz % fOSC = 100 kHz, 2.9V VDD 5.5V
SYNC
IOSYNC IISYNC IVSYNC Sync output current Sync input current Sync input voltage absolute limits 10 -0.5 VDD+0.5 10 20 A mA V VSYNC < 0.1 Volt
PWM
FPWM DMAX DMAX DMIN DMIN DMIN PWM Oscillation Frequency Maximum duty cycle Maximum duty cycle Minimum pulse width before pulse drop out Minimum duty cycle Minimum duty cycle 49 130 195 0 0 15 400 49.99 kHz % % nSec % % FPWM = fOSC/2, Stability as fOSC above fOSC = 30kHz fOSC = 800kHz VDD = 3.3V VFB > VNI, VSS > 2V VFB < VNI, VSS < 0.1V
2 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Electrical Characteristics - Continued
Symbol Parameter Min Typ Max Units Test Conditions
Reference
VREF VREF VREF VREF VREF IREF(SHORT) Reference output voltage Reference output voltage tolerance Reference output voltage tolerance Load regulation Line regulation Short circuit current (Test conditions: VDD = 3.3V) 0 85 70 VDD 5.5V) 25 0 65 1 1 -100 0 50 VDD-0.7 2 200 3 VDD-0.1 nA mV V dB MHz mA A V dB FOSC = 100 kHz VFB < VNI VFB > VNI VFB = 1.5V, VNI = 1.5V VFB = VCOMP, VNI = 1.5V 120 0.59 V V nSec nSec VCS = 0 to 1V step after blanking time 0.48VREF 0.50VREF 0.52VREF 2 2 1.2402 1 2 5 5 3 V % % mV mV mA TA = 25C, 2.4V TA = 25C, 2.4V -40C 2.4V TA VDD 0 < IREF < 0.1 mA 5.5V VREF = GND VDD VDD 5.5V 5.5V VDD 5.5V
85C, 2.4V
Current Sensing
VCS VCS VCS tDELAY
Usable control current sense range Current limit threshold Leading edge current sense blanking time Current limit delay to output (Test conditions: 2.9V
Error Amplifier
IFB or INI VFB - VNI VCM AVOL BW ISOURCE ISINK VCOMP PSRR
Input bias current Input offset voltage Common mode input range Open loop voltage gain Unity gain bandwidth Output current sourcing Output current sinking Output voltage range Power supply rejection
Soft Start
VSS(LOW) VSS(HI) ISS(HI) tF Soft start low output Soft start high output Soft start output current Soft start output fall time (Test conditions: 2.7V VDD 5.5V) 5 VDD-0.1 10 10 20 VDD mA A V V V V mV VSTATUS = 0.5V VSTATUS = (VDD - 0.5V) No load Sinking 2mA VSTATUS = LOW to HIGH transition VSTATUS = HIGH to LOW transition 2.5 10 0.1 VDD 20 10 V V A Sec VDD = 2.9V, VSENSE = 0V, VCS = 2.9V VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V CSS = 0.1F
Status Output
ISINK ISOURCE VSTATUS(HIGH) VSTATUS(LOW) VSENSE(THLH) VSENSE(THHL) VSENSE(HYST)
Output current sinking Output current sourcing High output voltage Low output voltage Sense input threshold for rising input Sense input threshold for falling input Sense input hysteresis
0.1 0.2 0.85VREF 0.85VREF 0.85VREF + 0.050 + 0.075 + 0.100 0.85VREF 0.85VREF 0.85VREF - 0.050 - 0.075 - 0.100 100 150 200
3 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Absolute Maximum Ratings*
V Input Voltage -0.3V to +250V -0.3V to +6V Supply Voltage, VDD Gate Drive Supply Voltage, VX2 -0.3 to +15V Operating Ambient Temperature Range -40C to +85C Storage Temperature Range -65C to +150C Power Dissipation @ 25C, SSOP 750mW Power Dissipation @ 25C, Plastic DIP 750mW
*All voltages referenced to SGND and PGND pins.
Ordering Information
Package Options 20-Pin SSOP Dice HV9606SP HV9606X
__________________________________________________________________________________________________________________
Pinout
VDD START STOP Vin REF SS SYNC RT SGND PGND STATUS SENSE FB COMP NI CA CB VX2 GATE CS
1
20
2
19
3
18
5
HV9606
4
17
SYNC - This I/O pin may be connected to the SYNC pin of other HV9606 circuits and will cause the oscillators to lock to the highest frequency oscillator. Synchronization to a master clock is possible by means of an open collector or open drain logic gate or optocoupler, provided the low duty cycle does not exceed 50%. If synchronization is utilized then a pull up resistor to VDD is required to overcome the effects of parasitic capacitance on the circuit board. The value of the resistor required will depend on the operating frequency and master clock duty cycle. RT - The resistor connected from this pin to SGND sets the frequency of the internal oscillator by setting the charging current for the internal timing capacitor. The PWM output frequency is one half the oscillator frequency. SGND - Common connection for all Logic and Analog circuits. PGND - Common connection for Gate Driver circuit. CS - This is the current sense input. Under normal operation the over current limit is triggered when the voltage on this pin exceeds 0.5VREF, however, current sensing is blanked during the first 85ns on time of the MOSFET to prevent false triggering during the turn on switching transition. The loop control operating peak current sense may be set to any level below 0.5VREF. GATE - This push-pull CMOS output is designed to drive the gate of an N-Channel power MOSFET. VX2 - This is the supply pin for the Gate Driver circuit and is generated by the Charge Pump VDD voltage doubler circuit. It should be bypassed to PGND with a capacitor, typically 0.1F. CA and CB - The charge pump circuit uses a capacitor (typically 0.01F) connected between these pins to generate the VX2 voltage. NI - High impedance non-inverting input of the error amplifier. COMP - The output of the error amplifier. FB - High impedance inverting input of the error amplifier. SENSE - This is the input pin to the supervisory circuit. On a rising input voltage the circuit changes state at a nominal 0.85VREF + 0.075V. When the input voltage is decaying the circuit changes state a nominal 0.85VREF - 0.075V. STATUS - This is the output of the supervisory circuit. When the sense-input voltage is high, this output is pulled up to VDD by a 10A current source and the Soft Start function is disabled. When the sense-input is low, this output is pulled low and it may be used to directly control the reset of a microprocessor or it may be used to drive an optocoupler or LED indicator.
16
6
15
7
14
8
13
9
12
10
11
Pin Description
VDD - This is the supply pin for the PWM Logic and Analog circuits. When the input voltage to the VIN pin exceeds the start voltage the input regulator seeks to regulate the voltage on the capacitor connected to this pin to a nominal 2.9V. After the PWM has started, the bootstrap supply will regulate this voltage to a nominal 3.3V or 5V. With VIN connected to PGND the circuit can be powered via this pin in the voltage range of 2.9V to 5.5V with a nominal 2.8V UVLO. START - The resistive divider from VIN sets the start-up regulator start voltage. STOP - The resistive divider from VIN sets the start-up regulator stop voltage. A low power sleep mode function may be implemented by pulling this pin to SGND. VIN - This is the startup linear regulator input. It can accept DC input voltages in the range of 15V to 250V. With START and STOP programmed to more than 20V, the leakage current on this pin is less than 6A at VIN = 20V. VREF - This pin provides a !1% tolerance reference voltage. SS - A capacitor connected to this pin determines the soft start time. Soft start may be initiated by a low VX2 voltage or an over current condition when supervisor circuit STATUS output is low. During short duration input interruptions when the output voltage does not decay below programmed limits, the supervisor circuit inhibits soft start to permit rapid recovery of the system.
4 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Functional Block Diagram
Vin Vdd Vdd UVLO C Oscillator Enable CA VX2 UVLO C Voltage Doubler CB
Regulator Start-Up Enable Regulator Programable Start/Stop Circuit
STOP
START
VX2
Oscillator
CLK Q _ D ___ Q CLR A C
GATE S Q CS R R PGND
Soft Start Supervisor Enable Circuit
R Soft Start Circuit
R
C
Current Limit
SGND
Vdd Bandgap Reference Generator 85 nS Delay
RT
SYNC STATUS SENSE
SS
VREF
NI
FB
COMP
Functional Description
The HV9606 is composed of several functional blocks. The operation of each of these blocks is described in the following sections. Programmable Start/Stop Control Circuit (Programmable Under Voltage Lockout and Hysteresis) The START/STOP control circuit is a novel version of a programmable under voltage lockout with programmable hysteresis circuit. It is novel, because it requires zero power (other than the current in the resistor divider) and keeps the startup regulator shut down until the START threshold voltage is exceeded, allowing the HV9606 to achieve its low input leakage current of <6A. One can think of the circuit as a transparent latch, such that its output is high when the START pin is above its threshold voltage and is latched when the STOP pin is at a voltage greater than the START pin voltage. It is unlatched when the STOP pin voltage falls below its threshold voltage and the START pin is below its threshold voltage. These operating conditions are met by using a voltage divider consisting of three resistors (see typical application circuit). The voltage drop on the resistor connected to ground controls the START voltage and the additional voltage drop on the middle resistor sets the hysteresis and controls the STOP voltage. Setting the value of the middle resistor to zero results in zero hysteresis. Provided the START and STOP pin input currents are negligible in comparison to the chosen resistor divider current, the resistor values may be calculated using the following equations: R3 = (VSTART / VIN-Start) x (VIN-Stop / IResistor) R2 = [(VSTOP / VIN-Stop) x (VIN-Stop / IResistor)] - R3 R1 = (VIN-Operating / IResistor) - R2 - R3 Where: VSTART is the START pin threshold voltage (nominal 7V) VSTOP is the STOP pin threshold voltage (nominal 7V) VIN-Start is the input voltage at which starting is desired VIN-Stop is the input voltage at which shutdown is desired IResistor is the resistor divider current (>1A)
5 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Functional Description - Continued
Start-Up Regulator The start-up regulator guarantees a maximum VIN pin leakage current of 6A at 20V at the VIN pin while it is inhibited by the START/STOP circuit. When the effective input voltage exceeds the programmed START voltage, the regulator is turned on and seeks to provide a nominal 2.9V at the VDD pin, which is the supply voltage for all internal circuitry within the HV9606 except the start/stop circuit. This regulator is capable of input voltages up to 250 Volts, which is the typical maximum arrester voltage limit used to provide protection on telephone wires. Due to the high voltage rating of the regulator the HV9606 can be used for applications operating from rectified AC mains up to 140Vrms. The regulator can supply a minimum of 5mA, which is sufficient to power the internal circuitry and provide gate drive power for the external MOSFET until the bootstrap circuit from the output of the PWM drives the voltage on the VDD pin higher than the regulator set point. This forces the regulator to turn off and reduce the input current at the Vin pin to leakage levels. The VDD pin is typically bypassed with a capacitor of at least 1F, which provides the peak currents required by the voltage doubler and in turn the gate driver for the external MOSFET. For low power applications the circuit may be operated without bootstrapping. Care should be taken to assure that the power dissipation in the regulator does not become excessive, as it might be if the input voltage is high and the gate drive energy required is high (operating at high frequency). Low voltage operation of the HV9606 is also possible by powering VDD from supply voltages of 2.9V to 5.5V. In these applications the Vin, START and STOP pins should be connected to SGND pin. When powering only via VDD, the START/STOP control is not available and the startup regulator circuit is not used. VDD Under Voltage Lockout To guarantee correct operation, internal circuitry is held reset by an under voltage lockout (VDD UVLO) until the regulator output voltage is at least 100mV below the startup regulator set point. To guarantee stable starting the VDD UVLO has a hysteresis of 100mV. Oscillator The oscillator circuit operates at twice the PWM output frequency. The frequency can be programmed in the range of 30kHz to 800kHz by means of a single resistor connected from the RT pin to SGND. For a given frequency the value of the resistor can be calculated using the following equation: RT = [(1 / fOSC) -1x10 ] / 42.6x10
-7 -12
Synchronization The SYNC pin is an input/output (I/O) port to a unique fault tolerant peer-to-peer and/or to master clock synchronization circuit. For synchronization the SYNC pins of multiple HV9606 based converters can be connected together and may also be connected to the open drain/collector output of an external master clock. When connected in this manner the oscillators will lock to the device with the highest operating frequency. The LOW duty cycle of an external master clock should not exceed 50%. When synchronized in this manner, a permanent logic HIGH or LOW condition on the SYNC pin will result in a loss of synchronization, but the HV9606 based converters will continue to operate at their individually set operating frequency. For this reason the SYNC pin is considered fault tolerant, since loss of synchronization will not result in total system failure. Depending on the cumulative parasitic capacitance on the SYNC pin when connected in the above manner a pull up resistor may be required from the SYNC pin to the VDD pin on each HV9606 based DC/DC converter circuit. The value of the resistor will depend on the cumulative parasitic capacitance and operating frequency. Voltage Doubler The HV9606 can operate on internal voltages ranging from 2.9V to 5.5V. It may be difficult to find power MOSFETs capable of operating with such low gate drive voltages. For this reason the HV9606 incorporates a voltage doubler circuit that generates a voltage on the VX2 pin that is approximately two times the VDD voltage. This circuit uses capacitive charge transfer methods and requires the connection of a capacitor (typically 0.01F) between the CA and CB pins as well as an energy storage capacitor (typically 0.1F) connected from the VX2 pin to PGND pin. The voltage doubler operates at the PWM output frequency. The gate driver output on the GATE pin operates from the VX2 voltage, logic level (5Volt) gate power MOSFETs may be used when VDD is bootstrapped at 3.3V or standard (10V) gate MOSFETs may be used when VDD is bootstrapped at 5V. VX2 Under Voltage Lockout To guarantee that sufficient gate drive voltage is available, an under voltage lockout circuit (VX2 UVLO) monitors the VX2 voltage. If the VX2 voltage drops below 4.5V the gate driver output of the PWM circuit is inhibited to prevent damage to the power MOSFET. This under voltage lockout has a hysteresis of 400mV to prevent spurious operation. Band Gap Reference The operating limits of all internal circuits, except the START/STOP circuit, are based on the !1% tolerance band gap reference voltage available on the REF pin. It is capable of delivering 100A for use by external circuitry without degrading the reference. A bypass capacitor of at least 0.1F should be connected from the REF pin to SGND pin.
6 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Functional Description - Continued
Current Sense and Current Limit Current sensing is accomplished by means of a resistor connected in series with the source of the external power MOSFET. There are two independent comparators monitoring the voltage drop across this resistor. One provides absolute peak current limiting at 0.5VREF and the other provides peak current feedback to the PWM control loop. Gate charge, capacitive loading and reverse recovery of output rectifier reflected to the drain of the power MOSFET results in high current spike at the positive leading edge of gate drive when the MOSFET is turning on. This can result in false tripping of the current limit comparator or incorrect operation of the control loop. To prevent this condition an 85nSec leading edge current sense blanking circuit is incorporated in the HV9606. This blanking period is sufficient in most applications to achieve stable operation. However, additional filtering of the MOSFET turn on current spike may be added by connecting a resistor in series with the (CS) current sense pin and a capacitor from the current sense pin to SGND pin. Error Amplifier The error amplifier has a minimum gain bandwidth of 1MHz. The inverting and non-inverting inputs are available respectively at FB and NI pins and the amplifier output is available at the COMP pin. Maximum application flexibility is provided to the designer by having all terminals of the error amplifier available. The design of the error amplifier prevents its output from saturating to the high rail (VDD) thus providing very fast slew recovery capability. Soft Start Control Circuit The soft start circuit provides a nominal constant current output of 10A at the SS pin for charging a capacitor connected to this pin. The instantaneous voltage on the SS pin determines the high limit of the error amplifier, thus forcing the PWM to start at minimum output duty cycle and slowly increase the duty cycle until stable closed loop operation is achieved. The value of the capacitor should be selected to achieve this stable closed loop operation before the voltage on the SS pin exceeds 1.2V at maximum output load on the DC/DC converter. Soft start can only be initiated if the STATUS output of the SUPERVISOR circuit is low. The SS pin is pulled low, discharging the capacitor and engaging soft restart whenever the VX2 UVLO detects a low gate drive voltage. PWM Circuit The current mode PWM circuit operates at one half the oscillator frequency with a duty cycle guaranteed not to exceed 50%. Its minimum pulse width (typically 130nSec) provides a wide dynamic control range especially when operating at low frequencies. For the dynamic control range required by a given application the maximum operating frequency can be determined using the following equations. tON = ( VIN(MAX) / VIN(MIN) ) x ( POUT(MAX) / POUT(MIN)) x DMIN fOSC = 2 fPWM < 1 / tON Where tON is the maximum gate drive output on time, VIN(MAX) and VIN(MIN) are the maximum and minimum input voltage, POUT(MAX) and POUT(MIN) are the maximum and minimum output power, DMIN is the worst case minimum gate drive output duty cycle (195nSec), fPWM is the maximum gate drive switching frequency and fOSC is the maximum oscillator frequency. Supervisor Circuit The designer may use this voltage monitor circuit for various applications. The supervisor circuit controls the function of the soft start circuit, which will be enabled when the STATUS output pin is in a low state. The STATUS output pin is low when the voltage on the SENSE pin is less than 0.85VREF - 100mV. The supervisory circuit can be used to monitor the output voltage of the DC/DC converter. When used in this manner the STATUS output pin may be used as a supply monitor and power on reset (POR) for a micro controller whenever the supply voltage decays to a programmed voltage level. Using it in this manner in a nonisolated topology, where the output voltage is used for bootstrapping VDD, it will inhibit soft start as long as the output is within programmed limits, thereby providing a rapid restart after a short duration input voltage dropout. This allows the minimization of both input and output capacitors for a given system hold up time requirement. In an Isolated topology, sizing the VDD capacitor for a hold up time greater than the output hold up time requirement will similarly permit the minimization of the input and output capacitors. The supervisory circuit can also be used as a high accuracy low input voltage detection and inhibit circuit by connecting the STATUS pin to the SS pin. Since the status pin has a 10A internal pull up it will double the charging current of the soft start capacitor, thus the soft start capacitor value needs to be doubled for the same soft start time. The SENSE pin may be connected through a resistor divider to any monitored voltage source (other than the output of the HV9606 based DC/DC converter) or to a logic output. When the voltage on the SENSE pin falls below 0.85VREF - 100mV, the SS pin will be pulled low, thereby inhibiting the gate drive output and shutting down the converter. The oscillator will operate even though the GATE output is held low and the SYNC I/O pin will maintain synchronization with other system components or provide a clock signal to the system. Shut Down / Inhibit Operation The HV9606 may be shut down or inhibited depending on the system requirements. Pulling the STOP pin down to SGND will shut down the HV9606, placing it in a zero power (leakage only) mode where even the oscillator is halted. This pull down may be accomplished with a discrete MOSFET, an optocoupler, or the open drain/collector output of a logic gate with at least 20V breakdown rating. Using this shut down method will cause the SYNC pin to be pulled low, thus synchronization of other components connected to the SYNC line will be lost. Provided the input voltage remains above the programmed stop threshold, inhibit of the PWM can be achieved by pulling the SS pin low to SGND, thereby forcing the gate drive output to a permanent low state and guaranteeing a soft restart when SS pin pull down is released. The internal start up regulator will power the HV9606 thus the oscillator will operate and the SYNC I/O pin will maintain synchronization with other system components or provide a clock signal to the system. This pull down could be accomplished with a discrete MOSFET, an optocoupler, or the open drain/collector output of a logic gate with at least a 5V breakdown rating.
7 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Application Information
Typical Semi-Isolated ISDN Circuit
T1
1.5W Flyback Converter
+ D3 C12 Isolated 40V D2 D1 R10 C10 C11 +5V +3.3V GND
R3 R2 C2 C9
1 VDD STATUS 20 2 START SENSE 19
Q1 To uP RESET pin.
R1 +48V C4
3
STOP
FB
18
C7
C8 R6
5
REF
HV9606
4
Vin
COMP
17
NI
16
6
SS
CA
15
C3
7 SYNC
C6
CB 14 VX2 13
R7
C1
R4
8 RT
C5
9 SGND PGND GATE 12 10 CS 11
M1
R8
R9 R5
GND
Typical Isolated ISDN Circuit
1.5W Isolated Flyback Converter
D4 T1 D3 C10 + Isolated 40V D2 D1 C8 C9 +5V +3.3V COM
R3 R2 C2
1 VDD STATUS 20
R12
2
START
SENSE
19
R1 +48V C4
3
STOP
FB
18
C7
R7 R6
6N135
5
HV9606
4
Vin
COMP
17
REF
NI
16
6
SS
CA
15
C3
7 SYNC
C6
CB 14 VX2 13
C11 R8
R13
C1
R4
8 RT
R10 TL431 R14
C5
9 SGND PGND GATE 12 10 CS 11
M1
R5 GND
R11
8 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Application Information
Typical Board Mounted Power (BMP) Supply
48V to 3.3V @ 20A Isolated Synchronous Forward Converter with Resonant Core Reset
Active Snubber Circuit
T1
M4 and M5
2 x Si4884DY
L1 + C10 C11 3.3V @ 20A -
D1
1N4148
R13 D2
R12 Q1 D3
D5 D4 M2 and M3
2 x Si4884DY
B320A
U2 R3 R2 C3
1 VDD
(+) IN
U1
STATUS 20
1.23V 31K
2
START
SENSE
19
R1 +48V C4
R10
3 STOP FB 18
COMP OUT Rf
C8
R6 R5
U3
MOC207
HV9606
4
Vin
COMP
17
R11 C9
5
REF
NI
16
LM3411
(-) GND
6
SS
CA
15
C5
7 SYNC
C6
CB 14 VX2 13
C1
C2
R4
8 RT
M1
IRF530S
C7
9 SGND GATE 12
R9
R7
10 PGND CS 11
R8 GND
Optional Connection to SYNC Pin of other HV9606 DC/DC Converters or Master Clock
9 4/15/2002-R.L2 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

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